Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide and conductive paths or interconnects made of conductive materials. Copper and copper alloys have recently received considerable attention as interconnect materials because of their superior electromigration and low resistivity characteristics. Interconnects are usually formed by filling copper by a deposition process in features or cavities etched into the dielectric interlayers. The preferred method of copper deposition is electroplating. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in sequential layers are electrically connected using vias or contacts.
In a typical interconnect fabrication process, first an insulating dielectric layer is formed on the semiconductor substrate. Patterning and etching processes are performed to form features such as trenches and vias in this insulating layer. Then, copper is electroplated to fill all the features after the deposition of a barrier and seed layer. After deposition and annealing of the copper layer, the excess copper (overburden) and barrier films left outside the cavities defined by the features have to be removed to electrically isolate the conductors within the cavities. Processes such as chemical mechanical polishing (CMP), chemical etching, electrochemical etching or polishing, or electrochemical mechanical etching or polishing techniques may be employed to remove the overburden copper layer.
This removal process needs to be performed in a highly uniform manner. If there are copper thickness non-uniformities present on the workpiece or if the removal process introduces removal rate non-uniformities, as the thickness of the overburden conductor such as copper is reduced by the removal process, residual copper may be left at various locations over the surface of the wafer. Continuation of the removal process to remove the residual copper regions may cause over-removal of copper from other regions which have already been freed of overburden copper. This causes copper loss from some of the features surrounding the areas containing the residual copper. As can be appreciated, such conductor loss from features causes resistance increases and defects and is not acceptable.
FIG. 1A shows an exemplary wafer with a non-uniform copper layer 12 with surface 14. Although not necessary, the non-uniformity of the copper layer 12 may be a result of an imperfect polishing or planarization process or a result of the copper deposition step. It is, for example, well-known that copper deposition processes often yield over-plated or super-plated regions, especially over the high aspect ratio and dense features. In these regions, the thickness of the copper overburden may be 500–5000 Angstrom or thicker compared to other parts of the wafer.
The copper layer 12 in FIG. 1A is formed on a dielectric layer 15, which is previously coated with a barrier layer 16. The copper layer 12 fills features 17 and the trench 18. As illustrated in FIG. 1A, due to the non-uniformity of the layer, copper layer has thin copper regions 22 with thin copper overburden layer and thick copper regions 24 with thick copper overburden layer. As shown in FIG. 1B, as the copper layer 12 is polished down using a removal process, thin copper regions 22 are polished down faster than the thick copper regions 24. As a result, material removal from the thin copper regions 22 is completed faster than the thicker copper regions, thus leaving residual copper regions 26 on the surface of the substrate. Residual copper region 26 represents a variable-thickness copper overburden (defined as the region between the dashed line and the surface 26A) and it has to be removed. FIG. 2 shows in plan view, an exemplary semiconductor wafer 10 having exemplary residual copper regions 26 distributed on the surface of the wafer. The residual copper regions 26 form conductive bridges between the features right under them.
As shown in FIG. 1C removal of residual copper regions by extending the duration of the traditional removal processes cited above may cause metal loss or dishing at the neighboring features which were previously freed from the copper overburden layer. This is also a common problem in CMP of Cu. Due to within die non-uniformity of Cu layers, there may be thick and thin regions of overburden Cu within a given die. Usually thick Cu region is over the dense small features. During CMP, thin Cu regions clear first. However, to clear the thick Cu regions the wafer is over-polished. During this overpolishing period, the regions which were already cleared off overburden Cu gets over processed giving rise to the dishing or erosion defects as mentioned above.